1. Technical Field
The present disclosure relates to mask design technology. More particularly, the present disclosure relates to using mask error enhancement factors (MEEF) in source mask optimization techniques.
2. Description of the Related Art
Minimum printed feature sizes in semiconductor devices become finer due to continuous requirements for ever higher performance and faster operation of the devices while reducing space consumption of information processing apparatuses. Thus, the minimum feature size of state of the art semiconductor devices reaches to about 22 nm or less. Masks having patterns of structures for semiconductor devices may be used for photolithography of layers included in semiconductor devices. Patterns for forming a semiconductor device are provided by the mask so as to expose the patterns of the mask with an adequate photo-imaging technology, including immersion exposure technologies. At current small feature sizes, photo-imaging technology is limited by a physically-driven degradation in image quality, and the associated resolution limitation makes it difficult to maintain adequate yields during manufacture of semiconductor devices with state-of-the-art feature sizes.
In general, Source Mask Optimization (SMO) makes best use of the limited optical resolution by initiating the design flow in the optical domain, thus identifying the best set of optical amplitudes that the mask can provide for printing the desired devices using the available optical resolution. However, a general behavior of optimization processes is that factors that are not explicitly addressed in the formulation will often tend to be driven to extreme/unfavorable values. In the SMO case, the key concern is that frequency-domain solutions will often be driven to large-DOF (depth of focus) patterns that unfortunately have excessive diffracting structure in, e.g., dark mask regions, making the masks overly difficult to fabricate within achievable tolerances.